Structure and Function of the Processor
The structure and function of the processor is the A Level Computer Science topic covering how a CPU's internal components, such as the control unit, ALU and registers, work together to fetch, decode and execute program instructions. It is a foundation topic of the Component 1 Computer Systems paper, underpinning later work on performance factors like cache and pipelining.
Before you start
No specific prerequisites - this is a good place to start.
Method
- Learn the roles of the control unit (CU), arithmetic logic unit (ALU) and registers (PC, MAR, MDR, CIR, ACC) before trying to trace any cycle.
- Write out the fetch stage in register transfer notation: MAR <- [PC], PC <- [PC]+1, MDR <- [[MAR]], CIR <- [MDR].
- Apply the decode stage: the CU interprets the opcode held in the CIR and generates the control signals needed for execute.
- Work through the execute stage for the specific instruction (e.g. LDD, ADD, STO), updating the ACC or memory as required.
- Link processor performance factors (clock speed, number of cores, cache size, pipelining) back to how quickly the fetch-execute cycle can repeat.
- Compare Von Neumann and Harvard architectures by checking whether instructions and data share one memory and bus system or use separate ones.
Worked example
A processor has a clock speed of 2.5 GHz, and each instruction takes an average of 5 clock cycles to complete. Calculate the number of instructions the processor can execute in one second.
- Convert the clock speed to hertz: 2.5 GHz = 2.5 x 10^9 cycles per second.
- Divide the cycles per second by the number of cycles needed per instruction: 2.5 x 10^9 / 5.
- Calculate the result: 2.5 x 10^9 / 5 = 5 x 10^8.
- Final answer: the processor can execute 5 x 10^8 (500 million) instructions per second.
Practice questions
Try each question, then tap to reveal the answer.
Exam-style questions
Written in the style of a A Level Computer Science exam paper, with a full mark scheme.
Explain what is meant by the 'fetch-decode-execute cycle', referring to the role of the Program Counter in your answer.
A processor has a 16-bit data bus and a 24-bit address bus. State the purpose of the data bus and the address bus, and calculate the maximum number of addressable memory locations this processor can access.
Describe what is meant by cache memory, and explain how the principle of temporal locality helps a cache improve processor performance.
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