Structure and Function of the Processor - Worksheets, Questions and Revision

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A-Level · Computer Systems

A1.1 Structure and Function of the Processor

OCR H446/01 · Calculators not allowed · about 110 minutes

Total Marks

Name: _______________________________ Date: ____ / ____ / ______

Answer ALL questions. Show all your working.

The Von Neumann model is the basis for most modern general purpose computer architectures.

(a)Define what is meant by the 'stored program concept'.(2)

(b)State the name of the CPU component that decodes fetched instructions, and the name of the component that carries out arithmetic and logic operations.(2)

(Total for Question 1 is 4 marks)

The Control Unit, Arithmetic Logic Unit and system clock each have a distinct role within the processor.

(a)State the purpose of the Control Unit (CU).(2)

(b)State the purpose of the Arithmetic Logic Unit (ALU).(2)

(c)State the purpose of the system clock in a processor.(2)

(Total for Question 2 is 6 marks)

The processor uses several special purpose registers during the fetch, decode, execute cycle: the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR) and the Accumulator (ACC).

(a)Complete the table by writing the correct register (PC, MAR, MDR or CIR) next to the function it performs.
i) Holds the address of the next instruction to be fetched.
ii) Holds the address currently being accessed in memory, for a read or a write.
iii) Holds data or an instruction that has just been fetched from memory, or is about to be written to memory.
iv) Holds the instruction that is currently being decoded or executed.(4)

(b)State the name of the register that holds the results of calculations performed by the ALU.(1)

(c)Explain why the Program Counter must be incremented during the fetch stage, even before the fetched instruction has been decoded.(3)

(Total for Question 3 is 8 marks)

The CPU is connected to main memory by a system of buses.

(a)State the purpose of the address bus.(1)

(b)State the purpose of the data bus.(1)

(c)State the purpose of the control bus.(1)

(d)The address bus is unidirectional, but the data bus is bidirectional. Explain why the data bus needs to be bidirectional.(2)

(e)State one consequence of increasing the width (number of bits) of the data bus.(1)

(Total for Question 4 is 6 marks)

The width of the address bus determines the maximum amount of memory a processor can directly address.

(a)A processor has a 16-bit address bus. Calculate the maximum number of individually addressable memory locations this allows. Show your working.(2)

(b)The processor is replaced with a version that has a 32-bit address bus instead. Calculate how many times larger the maximum addressable memory becomes.(2)

(c)State one other factor, besides the width of the address bus, that can limit the amount of RAM a computer actually uses.(1)

(Total for Question 5 is 5 marks)

A simple program is stored in main memory as follows:
address 100: LDD 200 (load the value directly from address 200 into the accumulator)
address 101: ADD 201 (add the value directly from address 201 to the accumulator)
address 102: STO 202 (store the value in the accumulator directly to address 202)
address 200: 15
address 201: 9
address 202: (currently empty)
The Program Counter starts at 100.

(a)Complete the trace table for the fetch stage of the instruction at address 100 (LDD 200) by giving the value placed in each register after each RTN step.
Step 1: MAR <- [PC] MAR = ?
Step 2: PC <- [PC]+1 PC = ?
Step 3: MDR <- [[MAR]] MDR = ?
Step 4: CIR <- [MDR] CIR = ?(4)

(b)State the register transfer notation for the execute stage of LDD 200, and give the resulting value held in the Accumulator (ACC).(2)

(c)Using the same method, state the value held in the Accumulator after the instruction at address 101 (ADD 201) has been executed.(2)

(d)State the value written to memory address 202 once the instruction at address 102 (STO 202) has been executed.(1)

(e)Convert the memory address 202 (denary) to hexadecimal. Show your working.(1)

(Total for Question 6 is 10 marks)

A processor has a clock speed of 3.2 GHz. On average, each instruction requires 4 clock cycles to complete.

(a)Calculate the number of instructions the processor can execute in one second. Show your working.(3)

(b)Explain why simply increasing clock speed indefinitely is not a practical way of improving a processor's performance.(3)

(Total for Question 7 is 6 marks)

Cache memory is used to reduce the average time the processor spends waiting for data from RAM.

(a)State what is meant by 'cache memory'.(2)

(b)The principle of locality of reference underpins how cache improves performance. Describe what is meant by temporal locality and spatial locality, and briefly explain how each helps cache improve performance.(4)

(Total for Question 8 is 6 marks)

Von Neumann and Harvard architectures organise memory and buses differently.

(a)Complete the table to compare Von Neumann and Harvard architectures.
i) Von Neumann - memory arrangement:
ii) Von Neumann - bus arrangement:
iii) Harvard - memory arrangement:
iv) Harvard - bus arrangement:(4)

(b)A manufacturer is designing the embedded processor for a domestic washing machine controller. Justify, with reference to the architectures compared in part (a), whether a Von Neumann or a Harvard architecture would be more suitable.(4)

(Total for Question 9 is 8 marks)

Many modern processors contain more than one core on a single chip.

(a)Describe what is meant by a multicore processor.(2)

(b)Explain two limitations of using a multicore processor to improve overall system performance.(4)

(c)State one type of task that would benefit significantly from running on a multicore processor.(1)

(Total for Question 10 is 7 marks)

Modern processors use pipelining to increase the rate at which instructions are processed.

(a)State the three main stages of the standard instruction pipeline.(3)

(b)Explain what is meant by pipelining in the context of processor performance.(2)

(c)A non-pipelined processor takes 4 clock cycles to fully execute one instruction (no overlap between instructions). A pipelined version of the same processor splits execution into 4 equal stages, one per clock cycle, so that once the pipeline is full, one instruction completes every clock cycle. Calculate the number of clock cycles required to execute a sequence of 100 instructions (i) without pipelining and (ii) with pipelining. Show your working.(3)

(d)Hence calculate the speedup factor achieved by pipelining for this sequence of instructions, to 2 decimal places.(1)

(Total for Question 11 is 9 marks)

A school is upgrading its computer suite and is choosing between two processor specifications for workstations that will mainly be used to run video editing software:
Processor X: clock speed 3.6 GHz, 4 cores, 8 MB L3 cache.
Processor Y: clock speed 4.2 GHz, 2 cores, 4 MB L3 cache.
The video editing software used is able to make use of multiple cores when rendering effects and exporting finished videos.
Discuss the factors that affect processor performance, and evaluate which of Processor X or Processor Y is likely to be more suitable for this video editing task. Justify your conclusion.

(Total for Question 12 is 9 marks)

The instruction ADD 300 adds the value stored at memory address 300 to the value already held in the accumulator. Assume the operand address (300) has already been placed in the CIR alongside the opcode.

(a)Using register transfer notation, write the sequence of statements for the fetch stage of any instruction.(4)

(b)Using register transfer notation, write the sequence of statements for the execute stage of the instruction ADD 300.(2)

(Total for Question 13 is 6 marks)

Mark scheme · A1.1 Structure and Function of the Processor

Question 1

(a) B1 program instructions and the data they operate on are held together, as binary values, in the same main memory oe
(a) B1 instructions are fetched from memory and executed one at a time, in sequence, by the processor oe
(a) Answer: Instructions and data are stored together, as binary, in the same main memory, and instructions are fetched and executed one at a time in sequence.
(b) B1 Control Unit (CU)
(b) B1 Arithmetic Logic Unit (ALU)
(b) Answer: Control Unit (decodes instructions); Arithmetic Logic Unit (arithmetic and logic operations).

Question 2

(a) B1 decodes the instruction held in the CIR oe
(a) B1 generates and sends the control signals needed to coordinate/manage the components of the CPU during execution oe
(a) Answer: The CU decodes instructions and generates the control signals that coordinate the CPU's components.
(b) B1 carries out arithmetic operations, e.g. addition, subtraction oe
(b) B1 carries out logical operations/comparisons, e.g. AND, OR, NOT, greater than oe
(b) Answer: The ALU performs arithmetic operations (e.g. addition) and logical operations/comparisons.
(c) B1 generates regular electrical pulses/a timing signal oe
(c) B1 used to synchronise the operations of the CPU's components, controlling the rate at which instructions are processed oe
(c) Answer: The clock produces regular timing pulses that synchronise the CPU's components and set the rate of processing.

Question 3

(a) B1 i) PC (Program Counter)
(a) B1 ii) MAR (Memory Address Register)
(a) B1 iii) MDR (Memory Data Register)
(a) B1 iv) CIR (Current Instruction Register)
(a) Answer: i) PC, ii) MAR, iii) MDR, iv) CIR
(b) B1 Accumulator (ACC)
(b) Answer: Accumulator (ACC)
(c) B1 the PC must hold the address of the next instruction to be fetched oe
(c) B1 incrementing it early ensures instructions are normally executed in the correct sequential order, one after another oe
(c) B1 unless the current instruction is a jump/branch instruction, in which case the PC is overwritten with a new address once that instruction is executed oe
(c) Answer: The PC is incremented early so it is ready to point to the next sequential instruction, unless a jump/branch later overwrites it.

Question 4

(a) B1 carries the memory address of the location to be read from or written to oe
(a) Answer: Carries the address of the memory location being accessed.
(b) B1 carries the actual data or instructions being transferred between the CPU and memory oe
(b) Answer: Carries the data/instructions transferred between the CPU and memory.
(c) B1 carries control signals, e.g. read/write signals, clock signals or interrupt signals, that coordinate/synchronise the transfer of data between components oe
(c) Answer: Carries control signals (e.g. read/write, clock, interrupt) that coordinate data transfer.
(d) B1 data must be able to travel from memory to the CPU, e.g. when a value is read/loaded oe
(d) B1 and from the CPU to memory, e.g. when a result is written/stored, whereas an address only ever needs to travel from the CPU to memory to specify a location oe
(d) Answer: Data must flow both ways (memory to CPU on a read, CPU to memory on a write), whereas addresses only ever travel from CPU to memory.
(e) B1 more bits/bytes of data can be transferred between the CPU and memory in a single operation/clock cycle, improving performance/throughput oe
(e) Answer: More data can be transferred per operation, improving performance.

Question 5

(a) M1 2¹⁶ shown as the method oe
(a) A1 65536, cao
(a) Answer: 65536 memory locations
(b) M1 2³² divided by 2¹⁶ (or 2^32-16) shown as the method oe
(b) A1 65536 times larger, cao (accept 2¹⁶)
(b) Answer: 65536 times larger
(c) B1 any one of: limitations of the operating system (e.g. a 32-bit OS may only support up to 4GB); the amount of RAM physically installed/available on the motherboard; cost oe
(c) Answer: For example, the operating system's own addressing limit, or the amount of RAM physically installed.

Question 6

(a) B1 MAR = 100, cao
(a) B1 PC = 101, cao
(a) B1 MDR = LDD 200, cao (the instruction stored at address 100)
(a) B1 CIR = LDD 200, ft from MDR
(a) Answer: MAR = 100, PC = 101, MDR = LDD 200, CIR = LDD 200
(b) M1 MAR <- [CIR operand] (i.e. MAR <- 200); MDR <- [[MAR]]; ACC <- [MDR], oe (any correct logic, ignore minor notation differences)
(b) A1 ACC = 15, cao
(b) Answer: ACC <- [MDR] where MDR holds the value at address 200; ACC = 15
(c) M1 ACC <- [ACC] + [MDR], where MDR holds the value fetched from address 201 (value 9), oe
(c) A1 ACC = 24, cao (ft from part b if a different value for ACC was carried forward consistently)
(c) Answer: ACC = 24
(d) B1 24, cao (ft from part c)
(d) Answer: 24
(e) B1 CA, cao (working shown, e.g. 202 = 12x16 + 10)
(e) Answer: CA

Question 7

(a) M1 3.2 GHz converted to Hz, i.e. 3.2 x 10⁹ cycles per second, oe
(a) M1 3.2 x 10⁹ divided by 4, correct method to find instructions per second oe
(a) A1 8 x 10⁸ instructions per second, awrt (accept 800,000,000 or 800 million), cao
(a) Answer: 8 x 10⁸ instructions per second (800,000,000)
(b) B1 a higher clock speed causes the processor to generate more heat, which risks damage or errors if not adequately cooled oe
(b) B1 a higher clock speed increases power consumption, which is a particular problem for battery powered/mobile devices oe
(b) B1 there are physical limits to how fast transistors can reliably switch, and overall performance may also be limited by other bottlenecks (e.g. RAM speed), so gains are limited oe
(b) Answer: Higher clock speeds increase heat and power consumption and are limited by physical switching speed and other system bottlenecks, so performance gains are not unlimited.

Question 8

(a) B1 a small amount of very fast memory, located on or very close to the CPU oe
(a) B1 used to store instructions and data that have recently been used, or are likely to be needed again soon, to reduce the time spent accessing slower RAM oe
(a) Answer: Cache is a small, very fast memory close to the CPU that stores frequently/recently used instructions and data, reducing waiting time for RAM.
(b) B1 temporal locality: if a memory location/instruction has recently been accessed, it is likely to be accessed again soon oe
(b) B1 so keeping recently used items in cache means future requests for them can be served quickly from cache rather than slower RAM oe
(b) B1 spatial locality: if a memory location is accessed, nearby/neighbouring locations are also likely to be accessed soon oe
(b) B1 so when data is fetched, nearby memory locations are also copied into cache, meaning they will already be present when needed oe
(b) Answer: Temporal locality: recently used items are likely to be reused soon, so cache keeps them ready. Spatial locality: nearby locations are likely to be used soon, so cache pre-loads them too.

Question 9

(a) B1 i) instructions and data are stored together in a single, shared main memory oe
(a) B1 ii) a single, shared bus system connects the CPU to memory, so an instruction and a data value cannot be transferred at exactly the same time oe
(a) B1 iii) instructions and data are stored in separate, independent memories oe
(a) B1 iv) separate bus systems connect the CPU to each memory, allowing an instruction and a data value to be transferred at the same time oe
(a) Answer: Von Neumann: shared memory, shared bus. Harvard: separate memories, separate buses (allowing simultaneous access).
(b) L2 (3-4): A clear, justified conclusion (Harvard or, if soundly reasoned, Von Neumann) that correctly applies at least two relevant features of the architectures (e.g. simultaneous instruction/data access, real-time response, program size/fixed function, cost, flexibility) to the specific context of an embedded washing machine controller. Correct terminology is used.
(b) L1 (1-2): A basic or partial answer, e.g. states which architecture is used in embedded systems generally, or identifies one relevant feature, without clearly applying it to the washing machine scenario.
(b) L0 (0): No relevant content, or the response does not address the scenario.
(b) Answer: Harvard architecture is generally more suitable, since simultaneous instruction/data access gives faster, more predictable real-time response for safety-relevant control; a well-justified case for Von Neumann on cost/simplicity grounds can also be credited.

Question 10

(a) B1 a single chip that contains two or more independent processing units (cores) oe
(a) B1 each core can carry out its own fetch, decode, execute cycle at the same time as the others oe
(a) Answer: A processor with two or more independent cores on one chip, each able to run its own fetch, decode, execute cycle simultaneously.
(b) B1 limitation 1 identified: not all software is written/optimised to make use of more than one core oe
(b) B1 expansion: some tasks are inherently sequential, where each step depends on the result of the previous one, so they can only run on a single core no matter how many are available oe
(b) B1 limitation 2 identified: coordinating/communicating between cores (e.g. sharing data, avoiding conflicts) introduces overhead oe
(b) B1 expansion: this overhead, together with heat and power demands of extra cores, means performance does not increase in direct proportion to the number of cores added oe
(b) Answer: Software must be written to exploit multiple cores, and sequential dependencies limit parallelism; coordination overhead and heat/power costs mean performance does not scale directly with core count.
(c) B1 any suitable highly parallelisable task, e.g. video rendering/encoding, running multiple independent applications at once, scientific/matrix simulations oe
(c) Answer: For example, video rendering, where independent frames/effects can be processed in parallel across cores.

Question 11

(a) B1 Fetch
(a) B1 Decode
(a) B1 Execute (oe; must be in this order for all 3 marks, otherwise max 1 mark for the correct set of names)
(a) Answer: Fetch, decode, execute
(b) B1 the fetch, decode and execute stages of successive instructions are overlapped, rather than one instruction fully completing before the next begins oe
(b) B1 so, once the pipeline is full, one instruction can be completed every clock cycle, increasing the overall rate/throughput of instruction processing oe
(b) Answer: Pipelining overlaps the stages of successive instructions so that, once full, one instruction completes per clock cycle, increasing throughput.
(c) B1 (i) 400 cycles, cao (100 x 4)
(c) M1 (ii) correct method shown: (number of stages - 1) + number of instructions, i.e. 3 + 100 oe
(c) A1 (ii) 103 cycles, cao
(c) Answer: (i) 400 clock cycles, (ii) 103 clock cycles
(d) B1 3.88, ft from part c (400 / 103), awrt
(d) Answer: 3.88 (2dp)

Question 12

Level 3 (7-9): A detailed, well-organised discussion that accurately explains at least three relevant performance factors (e.g. clock speed, number of cores, cache size, and/or software optimisation), applies them specifically to the figures given for Processor X and Processor Y, and reaches a clear, well-justified conclusion about suitability for the video editing task. Correct technical terminology is used consistently and accurately.
Level 2 (4-6): A reasonable discussion covering at least two relevant performance factors, with some application to the processor specifications given, reaching a conclusion. However, the discussion may be unbalanced, an important factor may be omitted, application to the scenario may be only partial, or the justification for the conclusion may be incomplete. Mostly correct terminology.
Level 1 (1-3): Basic or generic statements about one or two performance factors, with little or no application to the specific figures or scenario given. A conclusion, if present, is largely unsupported.
Level 0 (0): No relevant content, or the response does not address the scenario.
Indicative content:
- Clock speed determines the number of fetch, decode, execute cycles completed per second, so Processor Y's higher clock speed (4.2 GHz vs 3.6 GHz) allows it to complete more cycles per second on a single core
- Number of cores allows work to be split and processed in parallel; Processor X has more cores (4 vs 2)
- Since the video editing software can make use of multiple cores for rendering and exporting, these tasks are highly parallelisable, so having more cores available (Processor X) is likely to be more beneficial than a higher clock speed on fewer cores
- Cache size affects how much frequently used data (e.g. video frame buffers) can be held close to the CPU; Processor X's larger 8 MB cache should reduce the time spent waiting for slower RAM more than Processor Y's 4 MB cache, which is likely to help with large video files
- A counter-argument: for any part of the software that is single threaded (e.g. certain preview or user interface operations), Processor Y's higher clock speed per core may give faster performance on that part of the workload
- Overall performance depends on the combination of these factors together with how well the specific software is optimised, not on any single figure in isolation
- A justified conclusion, e.g. Processor X is likely to be more suitable overall, because its extra cores and larger cache are better matched to a workload (rendering/exporting) that is described as multi-core optimised, outweighing Processor Y's higher clock speed
- Credit an alternative conclusion (e.g. favouring Processor Y) if it is clearly and specifically justified using the figures and factors given