Computer Architecture, Assembly and the LMC - Worksheets, Questions and Revision

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A-Level · Computer Systems

A1.6 Computer Architecture, Assembly and the LMC

OCR H446/01 · Calculators not allowed · about 105 minutes

Total Marks

Name: _______________________________ Date: ____ / ____ / ______

Answer ALL questions. Show all your working.

Once an instruction has been fetched into the Current Instruction Register (CIR), it must be decoded before it can be executed.

(a)State what is meant by the 'opcode' part of a machine instruction, and what is meant by the 'operand' part.(2)

(b)Describe what happens during the decode stage of the fetch-decode-execute cycle.(2)

(c)State which CPU component is responsible for decoding the instruction.(1)

(Total for Question 1 is 5 marks)

Two assembly instructions are STA 250 (store the value in the accumulator directly to memory address 250) and BRA 50 (branch always to the instruction at address 50).

(a)Using register transfer notation, describe the execute stage of STA 250.(3)

(b)Using register transfer notation, describe the execute stage of BRA 50.(2)

(c)Explain how the execute stage of BRA 50 is able to change the normal sequential order in which instructions are fetched.(2)

(Total for Question 2 is 7 marks)

A processor's assembly language supports both immediate and direct addressing. LDM #45 loads the value 45 directly into the accumulator. LDD 45 loads, into the accumulator, whatever value is currently stored at memory address 45.

(a)Explain what is meant by immediate addressing.(2)

(b)Explain what is meant by direct addressing.(2)

(c)Memory address 45 currently holds the value 12. State the value that would be loaded into the accumulator by (i) LDM #45 and (ii) LDD 45, and (iii) explain why these two answers are different.(3)

(Total for Question 3 is 7 marks)

The same assembly language also supports indirect addressing (LDI) and indexed addressing (LDX), where LDX uses the index register (IX).

(a)Explain what is meant by indirect addressing.(2)

(b)Explain what is meant by indexed addressing, with reference to the index register (IX).(2)

(c)Memory address 60 holds the value 80. Memory address 63 holds the value 55. Memory address 80 holds the value 7. The index register (IX) currently holds the value 3. State the value loaded into the accumulator, and (where relevant) the effective address used, for (i) LDD 60, (ii) LDI 60, (iii) LDX 60.(4)

(Total for Question 4 is 8 marks)

The Little Man Computer (LMC) is a simplified model used to help understand how a real processor carries out the fetch-decode-execute cycle.

(a)State what the LMC is used to model.(1)

(b)Complete the table to match each part of the LMC model to its real computer equivalent.
i) Calculator:
ii) In-tray:
iii) Out-tray:
iv) Mailboxes:(4)

(c)State the number of mailboxes in the standard LMC model, and the range of values each mailbox can hold.(2)

(Total for Question 5 is 7 marks)

The table below sets out the LMC instruction set. Some cells have been left blank.

Opcode	Mnemonic	Meaning
1xx	(i)	Add the value in mailbox xx to the accumulator
(ii)	SUB	Subtract the value in mailbox xx from the accumulator
3xx	STA	(iii)
5xx	LDA	Load the value in mailbox xx into the accumulator
(iv)	BRA	Branch always: set the program counter to xx
7xx	(v)	If the accumulator is zero, set the program counter to xx
(vi)	BRP	If the accumulator is zero or positive, set the program counter to xx
901	(vii)	Input a value from the in-tray into the accumulator
(viii)	HLT	Stop the program executing

(a)Complete the table by giving the missing mnemonic or opcode for each of (i) to (viii).(8)

(b)Explain the purpose of a DAT instruction in an LMC program, giving an example.(2)

(Total for Question 6 is 10 marks)

The LMC program below inputs two numbers and outputs their sum.
00 INP
01 STA 99
02 INP
03 ADD 99
04 OUT
05 HLT
99 DAT 000
The program is run with the inputs 15, then 23, entered in that order.

(a)Complete a trace table showing the value in the accumulator (ACC) and in mailbox 99 immediately after each instruction (addresses 00 to 05) executes, and any value output.(6)

(b)State the value output by the program.(1)

(c)State the purpose of mailbox 99 in this program.(1)

(Total for Question 7 is 8 marks)

An LMC program is required that: inputs two numbers; subtracts the second number from the first; outputs the result if it is zero or positive; outputs 0 instead if the true result would be negative.

(a)Write LMC mnemonics for a program that meets this specification. Mailbox addresses do not need to be given, but the mnemonics must be in a logical, executable order.(6)

(b)Explain why the BRP instruction must be used at this point, rather than BRZ.(2)

(c)State the output of the program in part (a) for the input pairs (i) 8 then 8, (ii) 20 then 8, (iii) 8 then 20.(3)

(Total for Question 8 is 11 marks)

The LMC program below inputs a number and counts down from it, outputting each value in turn.
00 INP
01 STA 90
02 LDA 90
03 BRZ 08
04 OUT
05 SUB 91
06 STA 90
07 BRA 02
08 HLT
90 DAT 000
91 DAT 001
The program is run with the input 4.

(a)Complete a trace table showing the value in the accumulator and in mailbox 90 during each pass through the loop (addresses 02 to 07), all values output, and the point at which the program halts.(8)

(b)The instruction at address 07 (BRA 02) is changed to BRA 00. Explain the effect this would have if the program were run again with the input 4.(2)

(Total for Question 9 is 10 marks)

Discuss the extent to which the Little Man Computer (LMC) is a realistic model of how a modern processor carries out the fetch-decode-execute cycle. Your answer should consider registers, addressing modes and instruction sets.

(Total for Question 10 is 6 marks)

The LMC program below inputs two numbers and outputs their product, calculated by repeated addition.
00 INP
01 STA 90
02 INP
03 STA 91
04 LDA 95
05 STA 92
06 LDA 91
07 BRZ 15
08 LDA 92
09 ADD 90
10 STA 92
11 LDA 91
12 SUB 96
13 STA 91
14 BRA 06
15 LDA 92
16 OUT
17 HLT
90 DAT 000
91 DAT 000
92 DAT 000
95 DAT 000
96 DAT 001
The program is run with the inputs 3, then 4, entered in that order.

(a)Complete a trace table showing the values in the accumulator (ACC) and in mailboxes 90, 91 and 92 after each pass through the loop (addresses 06 to 14), and the final value output.(10)

(b)Explain, in your own words, how this program uses repeated addition to calculate the product of the two input values.(2)

(c)State one limitation of using this method to multiply two large numbers, and explain your answer.(2)

(Total for Question 11 is 14 marks)

Mark scheme · A1.6 Computer Architecture, Assembly and the LMC

Question 1

(a) B1 opcode: the part of the instruction that specifies which operation is to be carried out oe
(a) B1 operand: the part of the instruction that specifies the data value, or the address of the data, to be used by that operation oe
(a) Answer: The opcode specifies which operation to perform; the operand specifies the data (or its address) that the operation acts on.
(b) B1 the opcode held in the CIR is examined/interpreted oe
(b) B1 this identifies which operation is being requested and which circuits/components must be activated to carry it out during the execute stage oe
(b) Answer: The opcode in the CIR is examined so that the CPU can identify which operation is being requested and which components need to be activated to carry it out.
(c) B1 the Control Unit (CU)
(c) Answer: The Control Unit (CU).

Question 2

(a) M1 MAR <- 250, oe (the operand address is copied to the MAR)
(a) M1 MDR <- [ACC], oe (the value to be written is copied from the accumulator to the MDR)
(a) A1 [[MAR]] <- [MDR], oe (the value in the MDR is written to the memory location addressed by the MAR)
(a) Answer: MAR <- 250; MDR <- [ACC]; [[MAR]] <- [MDR]
(b) M1 PC <- 50, oe (the operand value from the CIR is copied directly into the PC)
(b) A1 correctly identifies that no memory read or write, and no change to the ACC, is needed to carry this out
(b) Answer: PC <- 50
(c) B1 normally the PC is incremented by 1 during fetch so that it points to the next instruction in sequence oe
(c) B1 the execute stage of BRA overwrites the PC with the operand address instead, so the next fetch reads the instruction at that new address rather than the following one oe
(c) Answer: Because the execute stage of BRA directly overwrites the PC with a new address, the next fetch reads from that address instead of the next sequential one.

Question 3

(a) B1 the operand given in the instruction is the actual data value to be used, not an address oe
(a) B1 correct reference to the example, e.g. LDM #45 loads the literal value 45 into the accumulator
(a) Answer: In immediate addressing the operand is the data value itself, e.g. LDM #45 loads the value 45 directly into the accumulator.
(b) B1 the operand given in the instruction is the address of the memory location holding the data to be used oe
(b) B1 correct reference to the example, e.g. LDD 45 loads whatever value is currently stored at address 45
(b) Answer: In direct addressing the operand is the address of the memory location holding the data, e.g. LDD 45 loads whatever value is stored at address 45.
(c) B1 (i) 45, cao
(c) B1 (ii) 12, cao
(c) B1 (iii) LDM treats its operand as the data itself, whereas LDD treats its operand as an address and fetches the value stored there, so the two instructions use the number 45 in completely different ways oe
(c) Answer: (i) 45 (ii) 12 (iii) LDM uses 45 as the value; LDD uses 45 as an address, giving the different value 12 stored there.

Question 4

(a) B1 the operand is the address of a memory location which itself holds the address of the data to be used (a pointer) oe
(a) B1 as a result, memory must be accessed twice to obtain the actual data value oe
(a) Answer: In indirect addressing the operand points to a memory location that itself contains the address of the data, so memory is accessed twice to reach the actual value.
(b) B1 the effective address used is found by adding the contents of the index register (IX) to the address given in the operand oe
(b) B1 this is useful for accessing a sequence of consecutive memory locations, e.g. the elements of an array, by changing IX rather than the instruction itself oe
(b) Answer: In indexed addressing the effective address is the operand address plus the value in IX, which allows a sequence of locations (e.g. an array) to be accessed by changing IX rather than the instruction.
(c) B1 (i) 80, cao (direct addressing: the value stored at address 60)
(c) B1 (ii) 7, cao (indirect addressing: address 60 holds 80, so the value at address 80 is loaded)
(c) B1 (iii) effective address = 63, cao (60 + IX, i.e. 60 + 3)
(c) B1 (iii) value loaded = 55, cao, ft from the effective address (the value stored at address 63)
(c) Answer: (i) 80 (ii) 7 (iii) effective address 63, value loaded 55

Question 5

(a) B1 a simplified model of how a (von Neumann) processor carries out the fetch-decode-execute cycle oe
(a) Answer: A simplified model of how a processor carries out the fetch-decode-execute cycle.
(b) B1 i) Accumulator (ACC)
(b) B1 ii) input device oe
(b) B1 iii) output device oe
(b) B1 iv) main memory/RAM oe
(b) Answer: Calculator = accumulator; in-tray = input device; out-tray = output device; mailboxes = main memory.
(c) B1 100 mailboxes, numbered 00 to 99
(c) B1 each mailbox holds a 3-digit number, from 000 to 999 oe
(c) Answer: 100 mailboxes (numbered 00-99), each holding a 3-digit number from 000 to 999.

Question 6

(a) B1 (i) ADD
(a) B1 (ii) 2xx
(a) B1 (iii) Store the value in the accumulator into mailbox xx oe
(a) B1 (iv) 6xx
(a) B1 (v) BRZ
(a) B1 (vi) 8xx
(a) B1 (vii) INP
(a) B1 (viii) 000
(a) Answer: (i) ADD (ii) 2xx (iii) Store the value in the accumulator into mailbox xx (iv) 6xx (v) BRZ (vi) 8xx (vii) INP (viii) 000
(b) B1 DAT reserves a mailbox to be used for storing a data value/variable, rather than as an executable instruction oe
(b) B1 valid example given, e.g. total DAT 0 reserves a mailbox labelled 'total', initialised to the value 0
(b) Answer: DAT reserves a mailbox for storing a data value rather than an instruction, e.g. total DAT 0 reserves a mailbox called total, initialised to 0.

Question 7

(a) B1 address 00 (INP): ACC = 15
(a) B1 address 01 (STA 99): mailbox 99 = 15
(a) B1 address 02 (INP): ACC = 23
(a) B1 address 03 (ADD 99): ACC = 38 (23 + 15)
(a) B1 address 04 (OUT): output = 38
(a) B1 address 05 (HLT): the program stops executing, consistent with all prior values
(a) Answer: 00 INP: ACC=15. 01 STA 99: mailbox99=15. 02 INP: ACC=23. 03 ADD 99: ACC=38. 04 OUT: outputs 38. 05 HLT: program stops.
(b) B1 38, cao, ft from part (a)
(b) Answer: 38
(c) B1 temporary storage for the first input value, so that it is not lost/overwritten when the second value is input, and can later be added to it oe
(c) Answer: It temporarily stores the first input value so it is not overwritten before it can be added to the second input.

Question 8

(a) B1 INP followed by STA to input and store the first number
(a) B1 INP followed by STA to input and store the second number
(a) B1 LDA (first value) then SUB (second value) to compute the difference in the accumulator
(a) B1 BRP used immediately after the subtraction, to branch directly to the output step when the difference is zero or positive
(a) B1 a fallback path, taken only when the branch is not taken, that loads 0 into the accumulator (e.g. via LDA of a mailbox holding DAT 0) before reaching the output step oe
(a) B1 OUT then HLT to output the accumulator and stop; DAT mailboxes correctly reserved for both inputs and the constant 0
(a) Answer: 00 INP / 01 STA 97 / 02 INP / 03 STA 98 / 04 LDA 97 / 05 SUB 98 / 06 BRP 09 / 07 LDA 99 / 08 BRA 09 / 09 OUT / 10 HLT / 97 DAT 0 / 98 DAT 0 / 99 DAT 0
(b) B1 BRZ only branches when the accumulator is exactly zero, so it would fail to branch whenever the difference is positive oe
(b) B1 BRP branches for both a zero and a positive accumulator, which correctly matches the requirement to output the true difference whenever it is zero or positive oe
(b) Answer: BRZ would only catch a zero result and would miss positive results, whereas BRP correctly branches for both zero and positive differences, matching the specification.
(c) B1 (i) 0, cao (8 - 8 = 0, BRP taken)
(c) B1 (ii) 12, cao (20 - 8 = 12, BRP taken)
(c) B1 (iii) 0, cao (8 - 20 = -12, BRP not taken, fallback outputs 0)
(c) Answer: (i) 0 (ii) 12 (iii) 0

Question 9

(a) B1 pass 1: ACC=4 then falls to 3 after the subtraction; output 4
(a) B1 pass 2: ACC=3 then falls to 2; output 3
(a) B1 pass 3: ACC=2 then falls to 1; output 2
(a) B1 pass 4: ACC=1 then falls to 0; output 1
(a) B1 mailbox 90 correctly tracked across passes as 4, 3, 2, 1, 0
(a) B1 on the fifth test at address 02/03, ACC (loaded from mailbox 90) = 0
(a) B1 the BRZ 08 condition is now met, so the program branches to address 08 rather than continuing the loop
(a) B1 final output sequence correctly stated as 4, 3, 2, 1 in that order, with no fifth output, and the program then halts
(a) Answer: Outputs, in order: 4, 3, 2, 1. Mailbox 90 takes the values 4, 3, 2, 1, 0 across the loop; once it reaches 0 the BRZ branches to HLT and the program stops.
(b) B1 execution would return to address 00 (INP) instead of address 02 at the end of each pass, so the program would request a brand new input value every time round the loop oe
(b) B1 this would overwrite the countdown value with whatever is newly input, so the program would no longer count down automatically from the original value oe
(b) Answer: The loop would jump back to INP instead of LDA 90, so a new value would be requested and stored on every pass, overwriting the countdown and breaking the intended automatic countdown behaviour.

Question 10

Level 3 (5-6): A well-balanced discussion covering similarities and differences across registers, addressing modes and instruction sets, with a clear, justified overall conclusion on how realistic the model is. Technical terms are used accurately throughout.
Level 2 (3-4): A discussion covering at least two of registers/addressing modes/instruction sets, with some valid comparison points, but a conclusion that is only partly justified, or an imbalance towards similarities or differences only.
Level 1 (1-2): Limited comparison, largely a description of the LMC or of a real processor rather than a comparison between them; little or no reference to registers, addressing modes or instruction sets.
Level 0 (0): No relevant content, or the response does not address the question.
Indicative content:
- The LMC uses a single general-purpose register (the accumulator/calculator), whereas a real processor has several distinct registers (PC, MAR, MDR, CIR, ACC, and sometimes an index register or general-purpose registers)
- The LMC's own cycle (fetch a mailbox, decode the opcode, execute it) mirrors the real fetch-decode-execute stages, so it is a valid simplified teaching model of the underlying process and of concepts such as branching and the role of the PC
- The LMC effectively only supports direct addressing of mailboxes for its ADD/SUB/STA/LDA instructions; it has no genuine immediate, indirect or indexed addressing, unlike a real processor which typically supports all of these
- The LMC's instruction set is very small (around ten instructions), compared with the much larger and more varied instruction sets of real processors
- LMC mailboxes store decimal numbers (000-999) directly as data or instructions, whereas real memory stores binary patterns, with instructions encoded in machine code as a binary opcode and operand
- The LMC has no concept of interrupts, pipelining, cache, or clock-driven timing, all of which significantly affect the performance of a real processor
- Overall the LMC is a useful, simplified model for understanding the sequence of fetch, decode, execute and basic branching, but it omits many features (multiple registers, full addressing modes, binary representation, performance features) present in a real processor, so it should be regarded as only a partial representation
- Credit either an overall conclusion (broadly realistic vs mostly unrealistic) provided it is supported by specific, accurate comparison points from at least two of the three areas named in the question