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GCSE · Computer Systems

P1.1 Systems Architecture

OCR J277 · Calculators not allowed · about 75 minutes

Total Marks

Name: _______________________________ Date: ____ / ____ / ______

Answer ALL questions. Show all your working.

Which of these best describes the purpose of the CPU?

(a)Identify the correct description of the purpose of the CPU.(1)

A) To store data permanently when the computer is switched off
B) To fetch, decode and execute instructions
C) To provide long term storage for the operating system
D) To convert analogue signals into digital signals

(Total for Question 1 is 1 mark)

State, in the correct order, the three stages of the fetch, decode, execute cycle.

(a)State the three stages of the cycle in the order they occur.(3)

(Total for Question 2 is 3 marks)

A simple program is stored in main memory as follows:
address 200: LDA 500
address 201: ADD 501
address 202: STA 502
address 203: HALT
The table below shows the contents of the Program Counter (PC), Memory Address Register (MAR) and Memory Data Register (MDR) during three consecutive fetch cycles. Some values are missing.
Cycle 1: PC (start) = 200, MAR = (i), MDR = (ii), PC (after increment) = 201
Cycle 2: PC (start) = 201, MAR = 201, MDR = ADD 501, PC (after increment) = (iii)
Cycle 3: PC (start) = 202, MAR = (iv), MDR = STA 502, PC (after increment) = 203

(a)Complete the missing value (i), the contents of the MAR in cycle 1.(1)

(b)Complete the missing value (ii), the contents of the MDR in cycle 1.(1)

(c)Complete the missing value (iii), the contents of the PC after cycle 2.(1)

(d)Complete the missing value (iv), the contents of the MAR in cycle 3.(1)

(Total for Question 3 is 4 marks)

Convert the denary number 173 to an 8 bit binary number.

(a)Show your working and give your final answer as an 8 bit binary number.(2)

(Total for Question 4 is 2 marks)

Convert the 8 bit binary number 11010110 to hexadecimal.

(a)Show your working and give your final answer as a two digit hexadecimal number.(2)

(Total for Question 5 is 2 marks)

Each of the following registers plays a specific role in the fetch, decode, execute cycle: MAR, MDR, PC, CIR, Accumulator. State the function of each register.

(a)State the function of each of the five registers: MAR, MDR, PC, CIR, Accumulator.(5)

(Total for Question 6 is 5 marks)

Describe how the fetch, decode, execute cycle uses registers to process an instruction.

(a)Describe the fetch, decode, execute cycle, referring to the registers involved.(4)

(Total for Question 7 is 4 marks)

A CPU has a clock speed of 3.2 GHz.

(a)Calculate the total number of clock cycles the CPU completes in 5 seconds. Show your working.(3)

(Total for Question 8 is 3 marks)

Clock speed is one factor that affects the performance of a CPU.

(a)Explain how increasing the clock speed of a CPU can improve its performance, and explain one reason why performance does not always increase proportionally as clock speed rises.(3)

(Total for Question 9 is 3 marks)

Many modern CPUs contain more than one core.

(a)Explain how having more than one core can improve the performance of a CPU.(3)

(Total for Question 10 is 3 marks)

CPUs contain a small amount of cache memory.

(a)Explain what cache memory is and explain how it can improve CPU performance.(3)

(Total for Question 11 is 3 marks)

A student is choosing a CPU for video editing software that has been optimised to make use of multiple cores. Two CPUs are available:
CPU X: clock speed 3.6 GHz, 4 cores, 8 MB cache.
CPU Y: clock speed 2.8 GHz, 8 cores, 12 MB cache.

(a)Using the data given, justify which CPU, X or Y, is likely to give better performance for this video editing task.(4)

(Total for Question 12 is 4 marks)

Not all computer systems are general purpose computers. Some are embedded systems.

(a)Define the term 'embedded system' and give two examples of a device that contains one.(3)

(Total for Question 13 is 3 marks)

Which of these is an example of an embedded system?

(a)Identify the example of an embedded system.(1)

A) A laptop running multiple applications
B) A smart thermostat that controls central heating
C) A desktop PC used for gaming
D) A web server hosting multiple websites

(Total for Question 14 is 1 mark)

Embedded systems are different from general purpose computer systems.

(a)Explain two ways in which an embedded system is different from a general purpose computer system.(4)

(Total for Question 15 is 4 marks)

The von Neumann architecture uses buses to transfer information between the CPU and memory.

(a)State the purpose of the address bus.(1)

(b)State the purpose of the data bus.(1)

(c)State the purpose of the control bus.(1)

(Total for Question 16 is 3 marks)

A CPU has an address bus that is 16 bits wide.

(a)Calculate the maximum number of individually addressable memory locations this allows. Show your working.(2)

(Total for Question 17 is 2 marks)

A gaming laptop has 8 cores and a clock speed of 2.0 GHz. A rival laptop has 4 cores and a clock speed of 3.5 GHz.

(a)Discuss, using your knowledge of the factors affecting CPU performance, why the 8 core laptop is not guaranteed to run all software faster than the 4 core, higher clock speed, laptop.(3)

(Total for Question 18 is 3 marks)

'Increasing the clock speed of a CPU is the best way to improve the overall performance of a computer system.'

(a)Evaluate this statement.(6)

(Total for Question 19 is 6 marks)

Describe, in detail, the fetch, decode, execute cycle, referring to the roles of the Program Counter, MAR, MDR, CIR, the Accumulator/ALU and the buses used to transfer information between the CPU and memory.

(a)Describe the fetch, decode, execute cycle in detail.(6)

(Total for Question 20 is 6 marks)

Mark scheme · P1.1 Systems Architecture

Question 1

(a) B1 B, fetch, decode and execute instructions
(a) Answer: B

Question 2

(a) B1 Fetch
(a) B1 Decode
(a) B1 Execute (oe, must be given in this order for all 3 marks; if order is wrong, award a maximum of 1 mark for the correct set of names)
(a) Answer: Fetch, decode, execute

Question 3

(a) B1 200, cao (the address held in the PC is copied to the MAR)
(a) Answer: 200
(b) B1 LDA 500, cao (the instruction stored at address 200)
(b) Answer: LDA 500
(c) B1 202, cao (PC incremented by 1 from 201)
(c) Answer: 202
(d) B1 202, cao (ft from (iii), copy of the PC at the start of cycle 3)
(d) Answer: 202

Question 4

(a) M1 Correct method shown, e.g. correct place values identified: 128, 64, 32, 16, 8, 4, 2, 1 with correct subset selected to total 173, oe
(a) A1 10101101, cao
(a) Answer: 10101101

Question 5

(a) M1 Binary split into two correct nibbles: 1101 and 0110, oe
(a) A1 D6, cao
(a) Answer: D6

Question 6

(a) B1 MAR, memory address register, holds the address of the memory location currently being read from or written to, oe
(a) B1 MDR, memory data register, holds the data or instruction being transferred to or from memory, oe
(a) B1 PC, program counter, holds the address of the next instruction to be fetched, oe
(a) B1 CIR, current instruction register, holds the instruction that is currently being decoded or executed, oe
(a) B1 Accumulator, stores the results of calculations or logic operations carried out by the ALU, oe
(a) Answer: MAR holds the address to be accessed; MDR holds the data/instruction transferred; PC holds the address of the next instruction; CIR holds the instruction being decoded/executed; Accumulator stores the results of ALU operations.

Question 7

(a) B1 Any four from: the address in the PC is copied to the MAR
(a) B1 the instruction stored at that address is copied from memory to the MDR
(a) B1 the PC is incremented so it holds the address of the next instruction
(a) B1 the instruction in the MDR is copied to the CIR
(a) B1 the instruction in the CIR is decoded (by the control unit)
(a) B1 the instruction is then executed and the cycle repeats (max 4 marks awarded overall, accept points in any logical order)
(a) Answer: PC to MAR, fetch from memory to MDR, PC incremented, MDR to CIR, decode, execute; repeat.

Question 8

(a) M1 3.2 GHz converted to Hz, 3.2 x 10⁹ cycles per second, oe
(a) M1 3.2 x 10⁹ x 5 (correct method to multiply by time in seconds)
(a) A1 1.6 x 10¹⁰ cycles, awrt (accept 16 000 000 000 or 16 x 10⁹), cao
(a) Answer: 1.6 x 10¹⁰ clock cycles

Question 9

(a) B1 clock speed is the number of fetch, decode, execute cycles the CPU can complete per second (measured in Hz/GHz), oe
(a) B1 increasing clock speed means more cycles, so more instructions, can be processed per second, improving performance, oe
(a) B1 however, increasing clock speed too far can cause the CPU to overheat/use more power, or performance may be limited by other components (e.g. RAM speed), so gains are limited, oe
(a) Answer: Higher clock speed means more instruction cycles per second, but heat/power/other bottlenecks limit further gains.

Question 10

(a) B1 each core can carry out its own fetch, decode, execute cycle independently, oe
(a) B1 so multiple instructions, tasks or threads can be processed at the same time (in parallel), oe
(a) B1 this increases the overall number of instructions completed per second, improving performance/throughput, oe
(a) Answer: Multiple cores allow multiple instructions/threads to be processed in parallel, increasing overall throughput.

Question 11

(a) B1 cache is a small amount of very fast memory located on, or very close to, the CPU, oe
(a) B1 it stores instructions and data that have recently been used or are likely to be needed again soon, oe
(a) B1 so the CPU can access this data more quickly than fetching it from RAM each time, reducing waiting time and improving performance, oe
(a) Answer: Cache is small, fast memory close to the CPU that stores frequently/recently used data, reducing the need to access slower RAM.

Question 12

(a) B1 CPU Y identified as likely to give better performance for this task
(a) B1 the software is optimised for multiple cores, so having more cores (8 vs 4) allows more threads/tasks to be processed in parallel, oe
(a) B1 the larger cache (12 MB vs 8 MB) means more data/instructions can be stored close to the CPU, reducing time spent accessing RAM, oe
(a) B1 although CPU X has a higher clock speed, this is less significant here because the software can make full use of extra cores rather than relying on a single fast core, oe
(a) Answer: CPU Y, because its extra cores and larger cache benefit multi-core optimised software more than CPU X's higher clock speed.

Question 13

(a) B1 a computer system built into a larger device or product to perform a specific, dedicated function, oe
(a) B1 example 1, e.g. washing machine, microwave, digital thermostat, traffic light controller, car engine management system (any suitable device)
(a) B1 example 2, a different suitable example to the one already given
(a) Answer: A computer system built into a device to perform a specific task, e.g. washing machine, digital thermostat.

Question 14

(a) B1 B, a smart thermostat that controls central heating
(a) Answer: B

Question 15

(a) B1 point 1 identified: dedicated/single function, oe
(a) B1 expansion: an embedded system is designed and programmed to carry out one specific task (e.g. controlling a washing machine's wash cycle), whereas a general purpose computer can run many different programs for many tasks, oe
(a) B1 point 2 identified: limited/fixed hardware resources, oe
(a) B1 expansion: embedded systems typically have limited processing power, memory and user interface to reduce cost, size or power consumption, because they only need to support one function, whereas general purpose computers have more powerful, flexible hardware to support varied software, oe
(a) Answer: Embedded systems have a single, dedicated function and limited/fixed hardware, unlike flexible, multi purpose general computers.

Question 16

(a) B1 carries the memory address of the location to be read from or written to, oe
(a) Answer: Carries the address of the memory location being accessed.
(b) B1 carries the actual data or instructions being transferred between the CPU and memory, oe
(b) Answer: Carries the data/instructions being transferred between CPU and memory.
(c) B1 carries control signals (e.g. read/write signals) that coordinate and synchronise the transfer of data between components, oe
(c) Answer: Carries control signals that coordinate data transfer between the CPU and memory.

Question 17

(a) M1 2¹⁶ shown as the method, oe
(a) A1 65536, cao
(a) Answer: 65536 memory locations

Question 18

(a) B1 any three from: not all software is written or optimised to make use of multiple cores; some programs are single threaded and can only use one core at a time
(a) B1 for a single threaded task, the laptop with the higher clock speed (3.5 GHz) may complete instructions faster on that one core than the 8 core laptop running at only 2.0 GHz
(a) B1 overall performance depends on a combination of factors (clock speed, number of cores, cache size, and how well software is optimised), not on core count alone (max 3 marks awarded overall)
(a) Answer: Performance depends on clock speed, core count and software optimisation together, so more cores does not guarantee faster performance for every task.

Question 19

Level 3 (5-6): Coherent, balanced discussion of at least three performance factors with a justified conclusion; correct terminology throughout.
Level 2 (3-4): Relevant discussion of clock speed and at least one other factor, with a conclusion, but may be unbalanced or lack detail.
Level 1 (1-2): Basic, list like statements about performance factors, conclusion may be missing or unsupported.
Level 0 (0): No relevant content.
Indicative content:
- Definition of clock speed and its effect on instructions processed per second
- Heat/power limits on increasing clock speed
- Effect of number of cores and software optimisation
- Effect of cache size on performance
- Effect of bus width on performance
- Overall balanced, justified conclusion

Question 20

Level 3 (5-6): Detailed, logically ordered description naming at least four registers and both address and data buses; correct terminology throughout.
Level 2 (3-4): Covers most stages, names some registers/buses, but missing some detail or minor inaccuracies.
Level 1 (1-2): Basic, incomplete description naming one or two stages or registers.
Level 0 (0): No relevant content.
Indicative content:
- PC to MAR, address bus
- Memory to MDR, data bus
- PC incremented
- MDR to CIR, decoded by control unit
- Execute using ALU/Accumulator, control bus coordinates transfer, cycle repeats

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